Publications by Andrea Guerrieri

DRSA: Accelerating Macro Placement on Commercial FPGAs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

PGAs are highly versatile devices, but their backend compilation process is significantly time-consuming. DynaRapid has demonstrated the potential to drastically reduce compilation times to mere seconds by leveraging macro-component-based design hierarchie ...

IEEE2025

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-or ...

Association for Computing Machinery, Inc2024

Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits

Andrea Guerrieri

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction ...

Institute of Electrical and Electronics Engineers Inc.2024

Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography

Andrea Guerrieri

FPGAs hold great promises for Post-Quantum Cryptography (PQC) hardware through the adoption of electronic design automation tools such as High-Level Synthesis (HLS). Previous works demonstrated how the combination of pragmas and code refactoring techniques ...

IEEE2024

Where is M-theory in the space of scattering amplitudes?

Andrea Guerrieri, João Miguel Augusto Penedones Fernandes

We use the S-matrix bootstrap to carve out the space of unitary, analytic, crossing symmetric and supersymmetric graviton scattering amplitudes in nine, ten and eleven dimensions. We extend and improve the numerical methods of our previous work in ten dime ...

Springer Nature2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

Assoc Computing Machinery2023

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

Dataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by their handshake communication protocol. Current pipelining solutions fail to account for logic ...

IEEE2023

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a ...

Assoc Computing Machinery2023

Numerical data for scattering amplitudes of Neutral Goldstone bosons in 4d

Andrea Guerrieri, Denis Karateev, Kelian Philippe Häring

Numerical data for scattering amplitudes of Goldstone bosons in d=4 obtained by solving various optimisation problems. The data is stored in .m files. Mathematica notebook is provided for loading and plotting the data. ...

Zenodo2023

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022