Keyvan Farhang Razi | EPFL Graph Search

Keyvan Farhang Razi received his BSc and MSc degree in Electrical Engineering from Amirkabir university of Technology, Tehran, Iran in 2016 and 2019 respectively. His field of activity and interest during his Bachelor of science education mainly covers analog circuits design using advanced HBT transistors and studying III-V compounds semiconductors as well as VLSI circuits design. In 2016, he joined photonics Research Lab (PRL) in Amirkabir university of Technology to carry out his bachelor diploma project under supervision of Prof. Hassan Kaatuzian.Subsequently, he became a member of RFIC laboratory at Amirkabir university of Technology as a Master of science student under supervision of Dr. Mohsen Moezzi in 2017. He conducted a great deal of research and projects in designing Radio-frequency integrated circuits and low-power analog CMOS integrated circuits during his MSc program. Also, he designed an elaborated RF-DC converter for RF energy harvesting applications in his MSc diploma project.He started his PhD education in Electrical Engineering at EPFL, Lausanne, Switzerland as a doctoral assistant in Biomedical Neuromorphic Microelectronic System (BNMS) group supervised by Dr. Alexandre Schmid in October 2019. Currently, he is working toward an interdisciplinary project which involves designing mixed-signal integrated circuits as well as neural signal processing to implement autonomous implantable patches for reliable closed-loop epilepsy control. The goal of this project is to provide autonomy and improve the quality of life of more than 60 million people who suffer from epilepsy.

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Keyvan Farhang Razi, Alexandre Schmid

A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-power 32-bit MIPS-based RISC processor which consists of five stages and supports three types of instructions. This work exhibits superiority over the existing seizure detectors since the RISC processor can be programmed by physicians to define different therapy options that are safe and efficient for each patient. Moreover, the patients have the opportunity of adjusting the seizure detection parameters by switching between different therapy options available under the permission of their physicians in order to enhance seizure detection performance. Seizure detection is performed by exploiting widely-used computational complexity-efficient time-domain features in conjunction with a feature ranking unit. The classification task is conducted by three logical functions which are defined to reach specific therapeutic goals such as rapid seizure detection and minimum false positive detections. Patients can dynamically adjust the critical seizure detection parameters such as sensitivity, specificity, and detection delay to make the medical device compatible with their current condition. The proposed programmable seizure detector is implemented on an ALTERA DE10-standard board with a Cyclone V FPGA and tested on 10 patients with 65 seizure events of the SWEC-ETHZ database from the Inselspital Bern which reveals a low dynamic power consumption of 0.78 mW which confirms its compatibility with low-power implantable devices.

IEEE2023

Computation Complexity Reduction Technique for Accurate Seizure Detection Implants

Keyvan Farhang Razi, Alexandre Schmid

An automatic seizure detection method from high-resolution intracranial-EEG (iEEG) signals is presented to minimize the computational complexity and realize real-time accurate seizure detection for biomedical implants. Complex signal processing on a large amount of iEEG signals captured via several electrodes is a crucial impediment in seizure detection when it comes to power consumption and real-time processing. Therefore, a subject-customized channel selection method correlated to a feature ranking unit is proposed to improve the computation efficiency and seizure detection accuracy by reducing the dimension of extracted features as well as the electrode channels. Nine popular time-domain features are extracted and ranked to constitute a customized feature subset. Subsequently, electrode channels are ranked with respect to the top four rank features obtained from the feature ranking unit. Then, the number of channels is optimized to reach the highest detection accuracy. The selected channels are compressed into a single channel to minimize the signal processing computation load. The suggested method is tested on seven patients with 37 seizure events from the SWEC-ETHZ dataset of the Bern University Hospital. The perfect sensitivity of 100%, the specificity of 92.98%, and the mean detection delay of 3.6 sec are achieved which outperform the state-of-the-art. In addition, the computation complexity is remarkably reduced which makes the presented method suitable for low-power real-time biomedical implants.

IEEE2022

Epileptic Seizure Detection With Patient-Specific Feature and Channel Selection for Low-power Applications

Keyvan Farhang Razi, Alexandre Schmid

An accurate epileptic seizure detector using intracranial electroencephalography (iEEG) recordings, suitable for low-power wearable/implantable applications, is presented. Eleven time-domain features with low hardware complexity are employed in the feature pool of the seizure detector. A novel two-step feature ranking algorithm based on maximum discrimination minimum redundancy (MDMR) is proposed to identify the most discriminating features in a patient-specific manner during a training phase. Subsequently, the top-ranked features are extracted in a two-stage energy-efficient architecture in which the second stage is activated by a controller to avoid unnecessary energy consumption imposed by multiple feature extraction during the long period of non-seizure states. The effective number of features which are continuously extracted is reduced in this work. Moreover, a patient-specific data reduction technique which selects the most informative and discriminating iEEG channels is also proposed. The presented channel selection technique reaches 68% data reduction on average for the tested patients and reduces the computational complexity. The proposed algorithm is implemented on Cyclone V FPGA of Terasic DE10-standard board. It is tested on twelve patients with short-term and long-term seizures from the Bern Inselspital dataset. The FPGA implementation results reveal an excellent sensitivity of 100% for all patients and remarkable specificity and detection delay improvement compared to the state-of-the-art. The average dynamic power consumption is 0.49 mW which is in the acceptable range for low-power wearable/implantable applications. In addition, a new figure-of-merit (FoM_SD) is defined to consider the major parameters of the seizure detectors. The outstanding FoM_SD of this work is 0.464 which outperforms the state-of-the-art.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Epileptic Seizure Detection With Patient-Specific Feature and Channel Selection for Low-power Applications

Keyvan Farhang Razi, Alexandre Schmid

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022