Person

Siang-Yun Lee

This person is no longer with EPFL

Biography

Siang-Yun Lee is a Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli. She graduated from the Department of Electrical Engineering of National Taiwan University in 2019, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis. Her research interests include logic synthesis and computational neuroscience.

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Siang-Yun Lee

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Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization