Siang-Yun Lee

This person is no longer with EPFL

Biography

Siang-Yun Lee is a Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli. She graduated from the Department of Electrical Engineering of National Taiwan University in 2019, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis. Her research interests include logic synthesis and computational neuroscience.

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Related publications (13)

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People doing similar research (10)

Siang-Yun Lee

Technology-Aware Logic Synthesis for Superconducting Electronics

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization

Technology-Aware Logic Synthesis for Superconducting Electronics

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization