Personne

Siang-Yun Lee

Cette personne n’est plus à l’EPFL

Biographie

Siang-Yun Lee is a Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli. She graduated from the Department of Electrical Engineering of National Taiwan University in 2019, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis. Her research interests include logic synthesis and computational neuroscience.

À propos de ce résultat

Cette page est générée automatiquement et peut contenir des informations qui ne sont pas correctes, complètes, à jour ou pertinentes par rapport à votre recherche. Il en va de même pour toutes les autres pages de ce site. Veillez à vérifier les informations auprès des sources officielles de l'EPFL.

Siang-Yun Lee

Graph Chatbot

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration