Publications by Kyojin Choo | EPFL Graph Search

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Kyojin Choo

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A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems

8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference

A 4.7μW switched-bias MEMS microphone preamplifier for ultra-low-power voice interfaces

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector

22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systems

27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC

A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor

Phase–frequency detecting time-to-digital converter