Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits

The aim of this research is to develop and to evaluate devices and circuits performances based on ultrathin nanograin polysilicon wire (polySiNW) dedicated to room temperature operated hybrid CMOS-"nano" integrated circuits. The proposed polySiNW device is a field effect transistor, where the transistor channel is a nanograin polysilicon wire, and its operation (programmation) is controlled by a silicon buried gate bias. The nanograin material is expected to offer interesting properties for single electron memory applications. The second main objective of the research is to realize and qualify a CMOS-polySiNW hybrid circuit, which offers novel functionalities and/or outperforming characteristics compared with state-of-the-art CMOS. Original approach consisting in hybridization, allows to bring out new functionalities (using polySiNW original characteristics), as well as much higher current level (provided by CMOS high current drive) than traditional nanoelectronic devices. Fabrication of the polySiNW device involves extensive technological developments for the deposition and the implantation of the ultra-thin 10nm nanograin polysilicon film. With the two-step deposition process consisting of an aSi deposition followed by a crystallization, a 6nm polysilicon film with grain sizes ranging from 5 to 20nm is realized. An original implantation process at 500°C is validated. Electrical characterization of the polySiNW devices shows ambipolar conduction (due to the Schottky nature of the source/drain contacts), and hysteresis effects linked to effective and reproducible electrical field assisted charge trapping in the polySiNW, at room temperature. Based on those two effects, a novel constant current bias scheme is proposed and applied to: low current measurement with less than 1pA resolution, new ultra-low power (few pWs) logic family, and memory. Finally, the nMOS-polySiNW technological hybridization opens the new field of the interfacing of polySiNW devices with other CMOS circuits or systems, but also the design of a hybrid negative differential resistance (NDR) circuit cell with some record performances. The fabrication of a hybrid NDR shows a peak-to-valley current ratio of more than seven decades, with a negative subthreshold slope of less than -10mV/decade, at room temperature.