MOSFET | EPFL Graph Search

The metal-oxide-semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. A metal-insulator-semiconductor field-effect transistor (MISFET) is a term almost synonymous with MOSFET. Another synonym is IGFET for insulated-gate field-effect transistor. The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925. The main advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with bipolar transistors (bipolar junction transistors/BJTs). In an enhancement mode MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In depletio

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

In the last decade the power consumption of electronic devices has increased for both static and active components. Following the Dennard's scaling rule, as long as the transistor sizes are reduced then the supply voltage (VDD) can also be scaled in order to increase the area density and maintain or improve the performances. However, scaling VDD and thus shifting the threshold voltage (Vth) of 60mV in a metal-oxide semiconductor field-effect transistor (MOSFET) increases the OFF state current (Ioff ) by a factor of 10 in the ideal case. The reason for this is that the inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of 60mV/decade. To overcome this limit, novel device concepts have been proposed and the tunnel field-effect transistor (TFET) is one of the most promising because it resembles a MOSFET and should enable to achieve sub-60mV/dec SS, low Ioff and small VDD. The aim of this thesis is to investigate the potential of TFETs by the fabrication and characterization of InAs/Si as p-channel and InAs/GaSb as n-channel device for a complementary TFET technology. III-V nanowires are grown via metal-organic chemical vapor deposition (MOCVD) and are integrated on Si(100) substrates using a novel technique called template-assisted selective epitaxy (TASE), which enables the fabrication of vertical and lateral III-V hetero-structure TFETs. Sub-40nm nanowire cross-section InAs/Si p-TFETs and InAs/GaSb n-TFETs in-plane on Si are demonstrated for the first time. The InAs/Si p-TFETs exhibit state-of-the art performances with an ON state current (Ion) of 4uA/um at VGS=VDS=-0.5V, ON/OFF ratio of 1x10E5 with SSavg of 70-80mV/dec at room temperature. The InAs/GaSb n-TFETs have an order of magnitude larger Ion but the SS is limited by the non-optimized gate-stack on InAs channel and by the depletion of the undoped GaSb source. Different operation regimes of TFETs are investigated by temperature-dependent measurements,Wentzel-Kramers-Brillouin (WKB) modeling and TCAD simulations, indicating that the switching region for InAs/Si is dominated by the presence of traps at the hetero-junction. The abruptness of the band-edges in InAs/GaSb is studied by the extraction of the conductance slope in fabricated p-n and p-i-n tunnel diodes.

EPFL2016

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

EPFL2012

Characterization and Modeling of Total Ionizing Dose Effects on Nanoscale MOSFETs for Particle Physics Experiments

Chunmin Zhang

Total ionizing radiation compromises electrical characteristics of microelectronic devices and even causes functional failures of integrated circuits. It has been identified as a potential threat to electronic components, especially those in high-energy physics experiments, space and avionic systems, and nuclear power plants. Among all harsh radiation environments, the future High Luminosity Large Hadron Collider (HL-LHC) at European Organization for Nuclear Research (CERN), is expected to have by far the highest levels of total ionizing dose (TID) with a peak of 1 Grad in the innermost electronics. Also, the number of pileup events per bunch crossing can reach up to 200, challenging trigger and data acquisition systems of its particle experiments. To reach long-term reliable operation, the HL-LHC will require innovative detecting and tracking systems with a higher level of granularity and bandwidth as well as robust radiation-tolerant front-end electronics. Complementary metal-oxide-semiconductor (CMOS) scaling allows extended circuit functionality and enhanced computing power. It also improves the TID tolerance of MOS field-effect transistors (MOSFETs) with relieved charge trapping related to ultrascaled gate dielectrics. To evaluate the potential use of highly scaled devices in the HL-LHC and eventually support circuit design for radiation-tolerant applications, this thesis characterizes and models the effects of TID up to 1 Grad on a commercial 28-nm bulk CMOS process. The characterization part focuses on evaluating measurable radiation effects and identifying dominant physical mechanisms. The modeling part aims at improving the understanding of the observed radiation effects and developing a design-oriented compact model for comprehensively accounting for them. Under various bias and temperature conditions, devices are irradiated, annealed, and tested after each irradiation and annealing step. Most of them demonstrate slight parametric shifts, confirming the very high TID tolerance of ultrathin gate dielectrics. TID-induced degradation in this technology primarily depends on charge trapping related to thick shallow trench isolation (STI) oxides. STI-trapped positive charges in nMOSFETs open parasitic channels along STI sidewalls and cause a significant increase in the drain leakage current, which however almost disappears after high-temperature annealing. STI-related charge trapping can even be strong enough to influence the central part of a narrow channel and is seen seriously degrading the performance of narrow-channel MOSFETs, which however can be relieved by shortening the channel. The TID-induced parasitic leakage current of nMOSFETs is modeled via a gateless charge-controlled transistor. To model the effects of TID on inversion operation, a generalized Enz-Krummenacher-Vittoz (EKV) charge-based MOSFET model is developed through the incorporation of radiation-induced trapped charges into the original EKV MOSFET model. Despite a small number of parameters, this model demonstrates an excellent match with measurement results over a wide range of device operation. The effects of TID on MOSFET characteristics are efficiently described by those few model parameters. This newly-developed radiation-aware EKV MOSFET model also demonstrates a width dependence of TID effects on 28-nm bulk MOSFETs, which can be explored for the model extension to a broad range of device dimensions even for a continuous range of TID levels.

EPFL2021