Full-wafer stencils fabricated by a DUV/MEMS process for high-throughput patterning of mesoscopic structures
Related publications (188)
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
We present a photonic meta-material with planar dielectric chiral structures on SU-8 realized using nanoimprint lithography (NIL). A Si template with chiral structure arrays was first fabricated by electron beam lithography (EBL) followed by reactive ion e ...
The fabrication of gold Fresnel zone plates, by a combination of e-beam lithography and electrodeposition, with a 30 nm outermost zone width and a 450 nm-thick structure is described. The e-beam lithography process was implemented with a careful evaluation ...
We demonstrate the nanofabrication of the transmission SU-8 gratings with periods from 200 nm (5000 lines/mm) to 1 lm (1000 lines/mm) with different trench depths for applications from near-infrared to deep-UV wavelength. The imprint property of SU-8 under ...
Stencil lithography is a surface patterning technique that relies on the local physical vapor deposition of material through miniaturized shadow mask membranes. It is extremely useful for the formation of patterns, mainly thin structured metal films, in si ...
We report on the fabrication and testing of a chip-scale plasma light source. The device consists of a stack of three anodically bonded Pyrex wafers, which hermetically enclose a gas-filled cavity in which electrodes are used to ignite a low power (≪500 mW ...
We report on the fabrication and testing of a chip-scale plasma light source. The device consists of a stack of three anodically bonded Pyrex wafers, which hermetically enclose a gas-filled cavity in which electrodes are used to ignite a low power (≪500 mW ...
One of the ultimate tasks for stencil lithography is the ability to fabricate arrays of structures with controlled dimensions on the nanometer scale precisely positioned on a suitable surface. The race to shrink feature sizes requires the limits of convent ...
We present nanostencil lithography as a new and parallel nanopatterning technique for batch fabrication of micro/ nanoelectromechanical systems (MEMS/NEMS) with high throughput and resolution. We use nanostencil lithography for the purpose of integrating n ...
We have fabricated new and robust nanostencil membranes for the surface patterning of 100-nm scale At wires on full wafer scale. The stencil membranes are mechanically reinforced with corrugations, making them more stable against accumulated stress. The ap ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007
The process comprises the step of deposition of a sensor and of a part or of the entirety of a treatment unit on a not necessarily planar conductive surface by a soft lithography technique. ...