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ReCast: Boosting tag line buffer coverage in low-power high-level caches "for free"

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ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This article presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple yet important task: Given the performance of an application on a small machine with a handful of cores, ES ...

2017

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This paper presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple, yet important task: given the performance of an application on a small machine with a handful of cores, EST ...

ACM Press2016

K Users Caching Two Files: An Improved Achievable Rate

Michael Christoph Gastpar, Saeid Sahraei

Caching is an approach to smoothen the variability of traffic over time. Recently it has been proved that the local memories at the users can be exploited for reducing the peak traffic in a much more efficient way than previously believed. In this work we ...

Ieee2016

How to Stop Under-Utilization and Love Multicores

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Iraklis Psaroudakis, Erietta Liarou

Hardware trends oblige software to overcome three major challenges against systems scalability: (1) taking advantage of the implicit/vertical parallelism within a core that is enabled through the aggressive micro-architectural features, (2) exploiting the ...

2015

Shared Frontend for Manycore Server Processors

Ilknur Cansu Kaynak

Instruction-supplymechanisms, namely the branch predictors and instruction prefetchers, exploit recurring control flow in an application to predict the applicationâs future control flow and provide the core with a useful instruction stream to execute in ...

EPFL2015

Confluence: unified instruction supply for scale-out servers

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instruction-supply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching tec ...

ACM Press2015

Caching (a pair of) Gaussians

Michael Christoph Gastpar, Guillaume Jean Op 't Veld

A source produces i.i.d. vector samples from a Gaussian distribution, but the user is interested in only one component. In the cache phase, not knowing which component the user is interested in, a first compressed description is produced. Upon learning the ...

2015

A Primer on Hardware Prefetching

Babak Falsafi

Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...

Morgan & Claypool2014

ADDICT: Advanced Instruction Chasing for Transactions

Anastasia Ailamaki, Pinar Tözün

Recent studies highlight that traditional transaction processing systems utilize the micro-architectural features of modern processors very poorly. L1 instruction cache and long-latency data misses dominate execution time. As a result, more than half of th ...

2014

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014