Publication
This thesis presents the fabrication and characterization of organic thin film transistors (TFTs) on flexible polymer substrates and the development of compliant stencil lithography to significantly improve the patterning resolution on full-wafer scale. Polymers and organic semiconductors have gained increasing attention during the last years. Today, organic semiconductors are envisioned as a viable alternative to traditional TFTs based on inorganic materials. Organic TFTs can be a solution for device flexibility, cost-efficient fabrication, low-temperature processing and large area patterning. However, up to now they cannot keep up with the performance of TFTs based on single-crystalline inorganic semiconductors because of their low switching speeds. Due to the sensitivity of polymers and organic semiconductors to solvents and high temperatures, stencil lithography is a promising patterning technique for such materials. Stencil lithography is based on the principle of the shadow mask technique, which is a parallel process with high spatial resolution down to submicrometer scale. It is a solvent-free patterning method without need of elevated temperatures. The stencil is aligned and clamped to the substrate and the required material is deposited through the stencil. Finally the stencil is removed, resulting in a patterned substrate. A typical stencil is made of low-stress silicon nitride (SiN) membranes supported by bulk silicon (Si). The membranes are released by combined dry and wet etching and contain design-specific micro- and nanoapertures. Stencil lithography was used to pattern titanium-gold (Ti-Au) wires on flexible polymer substrates. The wire resistivity was analyzed by 2-point and 4-point measurements and was found to be comparable with the resistivity of a Ti-Au thin film on a Si wafer. Stencil lithography was also applied to fabricate organic TFTs on a rigid Si substrate as the back gate contact. Polyimide (PI) or silicon dioxide (SiO2) was used as the dielectric layer while pentacene was tested as the organic semiconductor. Source-drain (S/D) Au top contacts were patterned by stencil lithography defining transistor channel lengths down to 5 µm. Pentacene TFTs with different film thicknesses were characterized on both dielectrics. The organic TFT fabrication on rigid Si substrates was used to evaluate pentacene films deposited on a PI dielectric. They have shown continuous pentacene films and similar characteristics compared to SiO2 as the dielectric layer. In a next step pentacene TFTs on a flexible 12 µm thin PI substrate were fabricated on full-wafer scale using a Si wafer as a rigid support. The gate contacts were patterned locally and PI was used as the dielectric material. Pentacene and S/D Au contacts were patterned by applying aligned full-wafer stencil lithography for channel lengths down to 2:5 µm. The yield of 72 pentacene TFTs was as high as 91.5 % and the average apparent mobility μ was (5.0 ± 0.7) · 10-2 cm2/Vs. The pen