Holographic memory design for a petaflop superconducting computer architecture

We will describe the role of holographic memory in a current research effort(1) that seeks to combine various advanced technologies to achieve petaflops scale computing within the next decade. In addition to holographic memory, the petaflop architecture combines superconductor Rapid Single Flux Quantum (RSFQ) logic, which can operate at 100 GHz within a cryogenic environment with power consumption less than 50 watts, a packer-switching optical network with a multi-level structure capable of providing interconnection among tens of thousands of ports with latencies of only 10 to 30 nanoseconds, Processor-in-Memory (PIM) technology, and a multithreaded hierarchical structure (see Figure 1) to allow the processors to access a high capacity memory while compensating for the latency problem inherent in such a system.