Dynamic Power Management: Design Techniques and CAD Tools
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Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing t ...
Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing ener ...
Subthreshold logic can dramatically reduce energy consumption, if the increased circuit delay is of secondary importance. To gain widespread adoption of this design technique (where V-dd < V-th), one of the important consideration is to improve the energy ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011
A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...
This paper discusses techniques, limitations and possible future developments of circuits based on transistors operated in the weak inversion (w.i.) mode, also called subthreshold mode. In analog circuits, w.i. is reached at very low current, but it is als ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009
has already been proven that analog emulation overcomes the speed limits of numerical simulators by means of a simple fixed-topology prototype. In order to enhance the modularity and the size of the emulated power system a dedicated platform based on a fie ...
Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...
This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...
This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose ...
The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...