A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication
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In this paper, a 4.6 GHz frequency synthesizer integrated circuit for Cesium-based miniature atomic clocks is presented. Based on a fractional-N phase-locked loop (PLL) with sigma-delta modulator, the chip features a frequency resolution below 10E-3 Hz at ...
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A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while ...
This paper presents a low-voltage low-power high-speed superregenerative receiver operating in the 2.4-GHz industrial-scientific-medical band. The receiver uses an architecture in which, thanks to the presence of a phase-locked loop, the quench oscillator ...
This paper presents the design, realization and characterization of a new hybrid A/D converter based on a combined incremental and cyclic conversion. The proposed implementation offers a configurable resolution, and permits to share the same hardware for t ...
In this study, we deal with the design and implementation of microsystems for electron spin resonance (ESR) applications. Three different microsystems are designed with different approaches for microwave magnetic field generation, ESR detection and sample ...
A negative-feedback scheme is applied to the gain stage of RC and LC ring oscillators to extend the frequency tuning range and to enhance the maximum oscillation frequency, respectively. This can be achieved without penalties in power consumption, supply v ...
In this paper we present Matlab analysis as well as CMOS implementation of an analog current mode Kohonen neural network (KNN). The presented KNN has been realized using several building blocks proposed earlier by the authors, such as: binary tree winner t ...
Following the trend in portable wireless communications, this dissertation explores new approaches to designing of power-critical building blocks in the elementary circuit level. Specifically, the work focuses on designs of baseband continuous-time Gm-C fi ...
A method and apparatus for a fast and automatic setting of the phase locked loop (PLL) output frequency that significantly improves linearity, locking range as well as spectrum purity, jitter and phase noise performances is disclosed. I n one embodiment, a ...
The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...