Publication

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

Related publications (33)

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Matthieu Berthomé

In this letter, we report the performance of high-kappa/metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Self-Assembled Liquid-Gated Zinc Oxide Nanowire Transistors

Vivek Pachauri

This thesis aims at the site-specific realization of self-assembled field-effect transistors (FETs) based on semiconducting Zinc oxide NWs and their application towards chemical and bio-sensing in liquid medium. At first, a solution based growth method for ...

EPFL2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high- ...

EPFL2011

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Giovanni Antonio Salvatore

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...

EPFL2011

Nanoengineered Silicon: Technology and Applications

Sandro Carrara, Lucia Baldi Unser

Silicon has been, and continues to be, the material support of integrated circuit (IC) technology-the enabling tool of one of the most impressive technological, industrial and social revolution of mankind. Silicon (both in monocrystalline and polycrystalli ...

2011

1T Memory Cell Based on PVDF-TrFE Field Effect Transistor

Mihai Adrian Ionescu, Nava Setter, Igor Stolichnov, Didier Bouvet, Giovanni Antonio Salvatore, Sebastian Riester, Roman Gysel

Interest in PVDF-TrFE copolymers as ferroelectric material for Memory application is driven by the prospect of having low cost, low operating voltage and fully organic device. Some previous studies reported FET designs using copolymers [refs 1,2] but none ...

2008

A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET–MOS hybrid architectures is also reported. The proposed process exploits an original low energ ...

2005