Resist-assisted assembly of single-walled carbon nanotube devices with nanoscale precision
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Semiconductor materials have given rise to today's digital technology and consumer electronics. Widespread adoption is closely linked to the ability to process and integrate them in devices at scale. Where flexibility and large surfaces are required, such ...
With technology scaling reaching the fundamental limits of Si-CMOS in the near future, the semiconductor industry is in quest for innovation from various disciplines of integrated circuit (IC) design. At a fundamental level, technology forms the main drive ...
The design of functional structures from primary building blocks requires a thorough understanding of how size, shape, and particle-particle interactions steer the assembly process. Specifically, for electrically conductive networks build from carbon nanot ...
WILEY-V C H VERLAG GMBH2019
The initial goal of this project was to determine by experimenting on a chip that where already design the ideal parameters for the dielectrophoresis of single walled carbon nanotubes. The epidemic blocking the access to the lab, the subject evolved to foc ...
2020
Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...
EPFL2016
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This paper reports the successful experimental demonstration of the localized growth of horizontal, dense carbon nanotube (CNT) arrays in situ and at the wafer scale. The selectivity and directionality of the CNT catalytic growth process along with the ade ...
Pergamon-Elsevier Science Ltd2014
As complementary metal–oxide–semiconductor (CMOS) scaling meets fundamental limitations, revolutionary device concepts and materials are urgently needed as alternatives or supplements to CMOS technology. Carbon nanotubes (CNTs), featuring extraordinary phy ...
EPFL2013
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We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p(+) GaAsSb raised source epitaxial re ...
IEEE2019
As the scaling of complementary metal-oxide-semiconductor (CMOS) technology is reaching fundamental limitations, novel device concepts and materials have started to be investigated to overcome the scaling challenges for integrated circuits. Graphene has be ...
EPFL2016
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The lack of selectivity toward a particular analyte has always been the primary concern regarding CNT-based gas sensors. For that reason, in here we present a gas discrimination strategy that focuses on the electrode-CNT junction. The junction is shown to ...
