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3D Integration Technology for Lab-on-a-Chip Applications

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3D Integration Technology for Lab-on-a-Chip Applications

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Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Methods and systems for high bandwidth chip-to-chip communications interface

Method for code evaluation using ISI ratio

Manycore Network Interfaces for In-Memory Rack-Scale Computing

A semi-analytical approach for optimized design of microchannel liquid-cooled ICs

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

On-chip Mass Sensing at the Physical Limits of Nanoelectromechanical Systems