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A CMOS Compatible Chip-to-Chip 3D Integration Platform

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A CMOS Compatible Chip-to-Chip 3D Integration Platform

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3D-Stacked CMOS SPAD Image Sensors: Technology and Applications

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

A reproducible method for μm precision alignment of PDMS microchannels with on-chip electrodes using a mask aligner

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

Post-cmos processing and 3d integration based on dry-film lithography

Design and Implementation of CMOS Image Sensors for Biomedical Applications

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration