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3.5-D Integration: A Case Study

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3.5-D Integration: A Case Study

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CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Clock Distribution Networks in 3-D Integrated Systems