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Defect states characterization of non-annealed and annealed ZrO2/InAlN/GaN structures by capacitance measurements

Related publications (36)

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Contacts and Environmental Effects in Two-Dimensional MoS2 Field-Effect Transistors

Dominik Sebastian Lembke

Two-dimensional (2D) semiconductors such as single- and few-layer molybdenum disulphide(MoS2) are promising building blocks for prospect flexible, transparent and low power electronics. Due to an electronic bandgap of the order of ~1.8 eV and atomic-scale ...

EPFL2014

Electrical Transport Properties of Single-Layer WS2

Andras Kis, Dumitru Dumcenco, Dmitry Ovchinnikov, Adrien Victor Allain

We report on the fabrication of field-effect transistors based on single layers and bilayers of the semiconductor WS2 and the investigation of their electronic transport properties. We find that the doping level strongly depends on the device environment a ...

Amer Chemical Soc2014

Junctionless nano-electro-mechanical resonant transistor

Mihai Adrian Ionescu, Sebastian Thimotee Bartsch

A junctionless Nano-Electro-Mechanical (NEM) resonator, comprising a highly doped conductive channel (4) connecting a drain (9) and a source (10) electrode and movably fixed by at least two ends (11, 11') acting as said source and drain electrodes, respect ...

2014

Ferroelectric tunnel fet switch and memory

Mihai Adrian Ionescu

A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junct ...

2013

ZrO2/InAlN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with InAlN Barrier of Different Compositions

Nicolas Grandjean, Jean-François Carlin

We report on InAlN/GaN heterostructure metal-oxide-semiconductor field-effect transistors (MOSHFETs) with an InAlN barrier layer of different compositions (x(InN) 13, 17, and 21%) and ZrO2 gate-insulator/passivation. Static measurements yielded higher drai ...

Iop Publishing Ltd2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

Institute of Electrical and Electronics Engineers2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high- ...

EPFL2011