Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache
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The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communica ...
To provide a scalable communication infrastructure for Systems on Chips (SoCs), Networks on Chips (NoCs), a communication centric design paradigm is needed. To be cost effective, SoCs are often programmable and integrate several different applications or u ...
Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are i ...
In this paper, we make the case for building high-performance asymmetric-cell caches (ACCs) that employ recently-proposed asymmetric SRAMs to reduce leakage proportionally to the number of resident zero bits. Because ACCs target memory value content (indep ...
Portable consumer devices are increasing more and more their capabilities and can now implement new multimedia algorithms that were resewed only for powerful workstations few years ago. Unfortunately, the original design characteristics of such algorithms ...
Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, ...
This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...
The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a p ...
This thesis presents a complete methodology for the digital calibration of analog circuits. It shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. In ...
Previous proposals for soft-error tolerance have called for redundantly executing a program as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar design, the extra workload from redundant execution induces a severe perform ...