Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors
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Software Transactional Memory (STM) promises to simplify concurrent programming without requiring specific hardware support. Yet, STM’s credibility lies on the extent to which it can leverage multi-cores to outperform sequential code. A recent CACM paper [8 ...
Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed mem ...
Homogeneous and heterogeneous NoC-based manycore MPSoCs are becoming widespread in many application areas. The diversity and spare network traffic characteristics generated by the IPs makes mandatory to provide certain Quality of Service (QoS) support for ...
In practice, concurrent programming systems based on message passing are often instantiations of the actor model. A popular implementation of this form of concurrency is the Erlang programming language. Erlang supports massively concurrent systems such as ...
One of the most celebrated results of the theory of distributed computing is the impossibility, in an asynchronous system of n processes that communicate through shared memory registers, to solve the set agreement problem where the processes need to deci ...
his paper determines the computational strenght of the shared memory abstraction (a register) emulated over a message passing system, and compares it with fundamental message passing abstractions like consensus and various forms of reliable broadcast. We i ...
A machining process based on Electro Discharge Machining (EDM) has been developed and allows producing flexible and low-cost tweezers-like grippers or grippers shaped for a specific application. It can be easily included in a micromanipulation setup and re ...
Concerns over rising soft-error rates in processor logic has led to numerous proposals for error tolerance mechanisms. In this paper, we examine the role of soft-error containment in a shared memory multiprocessor. We study a range of design alternatives b ...
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, programmers must choose from a spectrum of memory consistency models that reduce ...
Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full -fledged processors and large Field -Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application - specific coprocess ...