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Vertically stacked Si nanostructures for biosensing applications

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Explicit drain current model of junctionless double-gate field-effect transistors

Jean-Michel Sallese, Ashkhen Yesayan

This paper presents an explicit drain current model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of ...

Pergamon-Elsevier Science Ltd2013

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Coulomb blockade phenomenon in ultra-thin gold nanowires

Hoël Maxime Guérin

Ultra-thin gold nanowires with uniform diameters of 2 nm and lengths of over 100 μm are synthesized via the reduction of gold(III) chloride in an oleylamine matrix. The gold nanowires, dispersed on an oxidized substrate, are top-contacted with metallic ele ...

American Institute of Physics2012

Coulomb blockade in a granular material made of gold nanowires

Hoël Maxime Guérin

Uniform, 2 nm diameter gold nanowires were synthesized through the reduction of gold(III) chloride in an oleylamine matrix. They were top-contacted on a Si/SiO2 substrate with metallic electrodes to manufacture back-gated transistors. Due to thermal breaka ...

2012

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high- ...

EPFL2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011

Self-Assembled Liquid-Gated Zinc Oxide Nanowire Transistors

Vivek Pachauri

This thesis aims at the site-specific realization of self-assembled field-effect transistors (FETs) based on semiconducting Zinc oxide NWs and their application towards chemical and bio-sensing in liquid medium. At first, a solution based growth method for ...

EPFL2011

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

Mihai Adrian Ionescu, Luca De Michielis, Livio Lattanzio, Pierpaolo Palestri, Luca Selmi

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus ...

IEEE2011