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Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

Related publications (48)

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1T Capacitor-less DRAM cell based on asymmetric Tunnel FET design

Mihai Adrian Ionescu, Arnab Biswas

In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insu ...

2014

Technological development of high-k dielectric FinFETs for liquid environment

Mihai Adrian Ionescu, Didier Bouvet, Sara Rigante

This work presents the technological development and characterization of n-channel fully depleted high-k dielectric FinFETs (Fin Field Effect Transistor) for applications in a liquid environment. Herein, we provide a systematic approach based on Finite Ele ...

Pergamon-Elsevier Science Ltd2014

Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?

Andras Kis, Simone Bertolazzi, Wei Cao

Conventional floating-gate (FG) transistors (made with Si/poly-Si) that form the building blocks of the widely employed nonvolatile flash memory technology face severe scaling challenges beyond the 12-nm node. In this paper, for the first time, a comprehen ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Recent enhancements in BSIM6 bulk MOSFET model

Christian Enz, Yogesh Singh Chauhan, Maria-Anna Chalkiadaki

In this paper, we discuss the recent enhancements made in the BSIM6 bulk MOSFET model. BSIM6 is the latest compact model of bulk MOSFET from BSIM group which have body referenced charge based core. Junction capacitance model is improved over BSIM4 and is i ...

2013

Negative Capacitance Transistor

Alexandru Rusu

Silicon technology has advanced through the past four decades at exponential rate both in performance and productivity. Along with the miniaturization, the power demand grew also exponentially. New technologies are studied in order to develop switches that ...

EPFL2012

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Giovanni Antonio Salvatore

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...

EPFL2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011