Low Power Wake-up Receiver

With more devices becoming mobile, power consumption of communication becomes crucial. Wake-up receivers present an energy-ecient way of detecting incoming transmissions while at the same time the main radio can be fully powered down. After detection the rest of the circuit is activated in order to receive the transmission. Since the digital correlator is the main power consumer of a wake-up receiver, this work compares dierent correlator architectures in terms of their power performance. The correlator architectures are implemented in MATLAB for an analysis of their detection performance and later on in VHDL. A full front and back end implementation is made in order to extract the power performance of the architectures. Large parts of the work ow are automated, allowing to see immediately the impact of multiple parameters such as the sample resolution. Using an equation-based approach, the obtained power estimation is scaled into a sub-threshold region allowing to compare the power performance at very low voltage. The result of our architecture analysis shows that the positioning of the ip- ops is crucial to the power performance: combinational paths should be kept short, in contrast adding additional register to increase speed is benecial. Using large and complex logic decreases the power performance. For the analyzed correlator designs, the inversed structure splitting up the adder chain, which sums the correlation results, performed best. If noise is no issue, using a sample resolution of 1 bit leads to further improvement. Comparing the architectures in the sub-threshold region, fast architectures are less power benecial. A pipelined structure seems to oer a good trade-o between combinational circuit and amount of registers used and has therefore the lowest power consumption.