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4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

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4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

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1T Capacitor-less DRAM cell based on asymmetric Tunnel FET design

Single event upset mitigation in low power SRAM design

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Beyond Scaling

Negative Capacitance Transistor

Process Variation and Leakage Power