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Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Related publications (42)

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A 73% Peak PDP Single-Photon Avalanche Diode Implemented in 110 nm CIS Technology With Doping Compensation

Edoardo Charbon, Claudio Bruschini, Ekin Kizilkan, Utku Karaca, Myung Jae Lee

In this article, we present 10 mu m diameter SPADs fabricated in 110 nm CIS technology based on an N (+) /HVPW junction, with enhanced sensitivity at short wavelengths. To reduce tunneling noise due to the highly-doped layers in the process, a doping compe ...

Ieee-Inst Electrical Electronics Engineers Inc2024

A novel approach for SPICE modeling of light and radiation effects in ICs

Chiara Rossi

Modeling the interaction of ionizing radiation, either light or ions, in integrated circuits is essential for the development and optimization of optoelectronic devices and of radiation-tolerant circuits. Whereas for optical sensors photogenerated carriers ...

EPFL2021

Gradient flow emulation using drift diffusion processes

Sanket Sanjay Diwale

The present invention concerns a method of emulating gradient flow for solving a given problem as a charge distribution in a device (1) comprising: first type charge carrier regions (5) interfacing a second type charge carrier region (11) thereby forming c ...

2021

Prediction of optically-triggered amplification in phototransistor with SPICE circuit simulators

Jean-Michel Sallese, Chiara Rossi

Modeling of optoelectronic devices involves long and complex numerical simulations, usually performed with TCAD tools. Numerical simulations provide accurate results for a single device but are not feasible when dealing with a full circuit comprising sever ...

SPIE-INT SOC OPTICAL ENGINEERING2020

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâs la ...

EPFL2019

Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi, Maxime Victor Thammasack, Tsung-Han Lin, David Baudouin

The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this br ...

Amer Chemical Soc2017

Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, wit ...

IEEE2017

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits ...

EPFL2016

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Jian Zhang

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. W ...

EPFL2016

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Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

Institute of Electrical and Electronics Engineers2016