Graphene Negative Differential Resistance Circuit With Voltage-Tunable High Performance at Room Temperature
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The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...
The design of distributed amplifiers in a CMOS process is investigated. In particular, the impact of parasitic elements from the transistors and from interstage inductors is studied. A methodology for determining an optimum design, including the number of ...
A negative-feedback scheme is applied to the gain stage of RC and LC ring oscillators to extend the frequency tuning range and to enhance the maximum oscillation frequency, respectively. This can be achieved without penalties in power consumption, supply v ...
A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 um CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixt ...
In this paper we present Matlab analysis as well as CMOS implementation of an analog current mode Kohonen neural network (KNN). The presented KNN has been realized using several building blocks proposed earlier by the authors, such as: binary tree winner t ...
We present local and non-local electron transport measurements on individual multi-wall nanotubes for bias voltages between 0 and about 4 V. Local current–voltage characteristics are quite linear. In contrast, non-local measurements are highly nonlinear; t ...
A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital converter (ADC) has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tune ...
Following the trend in portable wireless communications, this dissertation explores new approaches to designing of power-critical building blocks in the elementary circuit level. Specifically, the work focuses on designs of baseband continuous-time Gm-C fi ...
This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...
A fast modulator for a dynamic supply linear RF amplifier has been integrated in a 0.35-μm CMOS technology. The use of this modulator with an external linear power amplifier (PA) allows to maintain its efficiency at a higher level than it would with the sa ...