Publication

The Programmable Logic-in-Memory (PLiM) Computer (Invited)

Related publications (42)

Endurance Management for Resistive Logic-In-Memory Computing Architectures

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon

Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low writ ...

Ieee2017

A PLiM Computer for the Internet of Things

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon

Emerging applications are dramatically changing computer architecture requirements, with a shift toward big data that is processed using simple computations. A programmable logic-in-memory (PLiM) computer can allow memory cells to perform primitive logic o ...

2017

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Paolo Ienne, Grace Zgheib, Yu Lin, Wei Li

The And-Inverter Cone has been introduced as an alternative logic element to the look-up table in FPGAs, since it improves their performance and resource utilization. However, further analysis of the AIC design showed that it suffers from the delay discrep ...

ACM2017

Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices

David Atienza Alonso, Abdulkadir Akin, Ivan Beretta, Alessandro Antonio Nacci

The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs), which are often employed t ...

Assoc Computing Machinery2016

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for ...

2016

An MIG-based Compiler for Programmable Logic-in-Memory Architectures

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on r ...

Ieee2016

EU COST Action IC1401-Pushing the Frontiers of Memristive Devices to Systems

Sandro Carrara

European Union COST Actions provide the opportunity for researchers who are geographically dispersed to work together towards an ambitious, multidisciplinary goal, whilst learning from each other and avoiding effort duplication. This paper gives a brief ov ...

Ieee2016

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