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A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

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A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

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Die-Level TSV Fabrication Platform for CMOS-MEMS Integration

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling

Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries

Thermal-Aware Design of of 3D ICs with Inter-Tier Liquid Cooling

Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks