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This paper describes a converter which configures itself to increase power transfer and decrease losses. The system controls its three timing variables by three loops in a stable manner. A time domain state-space averaging model is used to design the system. This reduces the necessary components, and therefore the power consumption. The system is implemented in 0.18 µm CMOS technology with ultra-low power circuits. The converter has a 52% efficiency with just a 15 mV input voltage. It follows changes in electrical specifications of a harvester, in order to increase the system's output power.
David Atienza Alonso, Miguel Peon Quiros, José Angel Miranda Calero, Hossein Taji
David Atienza Alonso, Alexandre Sébastien Julien Levisse, Tomas Teijeiro Campo, Silvio Zanoli, Flavio Ponzina