Publication

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Related publications (123)

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

, ,

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the po ...

2018

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread ...

2018

In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-fin ...

IEEE2018

, ,

Amongst 2-dimensional (2D) semiconductors of the transition-metal di-chalcogenide (TMDC) family [1], tungsten diselenide (WSe2) has shown ambipolar behavior [2], [3] coupled with high carrier mobility [4] and CMOS-like devices have been experimentally demo ...

IEEE2018

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Jean-Michel Sallese, Christophe Lallement

Transconductance efficiency (g(m)/I-D) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of g(m)/I-D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully deple ...

2018

, , ,

We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P + /Deep N-well junction with a circular shape, for whi ...

2018

Tunnel fet based non-volatile memory boosted by vertical band-to-band tunneling

Mihai Adrian Ionescu, Saurabh Tomar, Arnab Biswas

A tunnel field effect transistor (TFET), including a source region, a gate region, a channel region, and a drain region, the gate region including a gate stack, wherein an area of the source region that is facing the channel region is overlapped by the gat ...

2018

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti, Jeremy Hugues-Felix Constantin

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

The semiconductor industry, governed by the Moore's law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor ...

EPFL2017

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

Matthias Bucher, Mathieu Yves Hervé Coustans

Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, wit ...

IEEE2017