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Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling

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This paper introduces the concept of size-aware sharding to improve tail latencies for in-memory key-value stores, and describes its implementation in the Minos key-value store. Size-aware sharding distributes requests for keys to cores according to the si ...

USENIX ASSOC2019

The mismatch between household electricity consumption and solar energy production is a key issue for the fast deployment of this technology in a low-voltage grid. Namely, as high photovoltaic generation occurs during the day while the load remains low, th ...

2018

Nowadays, the ubiquity of smart appliances in our everyday lives is increasingly strengthening the links between humans and machines. Beyond making our lives easier and more convenient, smart devices are now playing an important role in personalized health ...

EPFL2018

The rise of web-scale services has led to a staggering growth in user data on the Internet. To transform such a vast raw data into valuable information for the user and provide quality assurances, it is important to minimize access latency and enable in-me ...

EPFL2017

, , , ,

To provide low latency and high throughput guarantees, most large key-value stores keep the data in the memory of many servers. Despite the natural parallelism across lookups, the load imbalance, introduced by heavy skew in the popularity distribution of k ...

2016

Key/Value-enabled Flash Memory for Complex Scientific Workflows with On-line Analysis and Visualization

Stefan Eilemann, Alessandro Curioni, Peter Morjan, Blake Fitch, Bernard Metzler, Lars Schneidenbach, Ralph Bellofatto, Peter Kaltstein

Scientific workflows are often composed of compute-intensive simulations and data-intensive analysis and visualization, both equally important for productivity. High-performance computers run the compute-intensive phases efficiently, but data-intensive pro ...

Ieee2016

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

David Atienza Alonso, Giovanni Ansaloni, Pablo Garcia del Valle, Soumya Subhra Basu

This paper introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimize energy consumption. In this scenario, the reliability of ...

Inst Engineering Technology-Iet2016

An Analysis of Load Imbalance in Scale-out Data Serving

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

Despite the natural parallelism across lookups, performance of distributed key-value stores is often limited due to load imbalance induced by heavy skew in the popularity distribution of the dataset. To avoid violating service level objectives expressed in ...

2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Andreas Peter Burg, Adam Shmuel Teman, Luca Benini, Pascal Andreas Meinerzhagen

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Sort vs. Hash Join Revisited for Near-Memory Execution

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Nooshin Sadat Mirzadeh

Data movement between memory and CPU is a well-known energy bottleneck for analytics. Near-Memory Processing (NMP) is a promising approach for eliminating this bottleneck by shifting the bulk of the computation toward memory arrays in emerging stacked DRAM ...

2015