3D-Stacked CMOS SPAD Image Sensors: Technology and Applications
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Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...
New advances in the field of image sensors (especially in CMOS technology) tend to question the conventional methods used to acquire the image. Compressive Sensing (CS) plays a major role in this, especially to unclog the Analog to Digital Converters which ...
Since the first introduction of digital cameras, the camera market has been taking tremendous interest from many fields. This trend has even accelerated when the cost, size, and power consumption of such devices were reduced with the introduction of camera ...
In recent years, modern imaging sensors and systems have become increasingly complex following the growing demand for high-quality and high-resolution imaging. Commercially available sensors having 30-40 mega-pixel resolutions are common nowadays, while pr ...
An integrated chip for DNA hybridization detection was realized in a standard CMOS process: it hosts 80 biosensors subdivided in 2 channels, as well as D/A and A/D converters for electrical stimulation and readout. A microfluidic system, bonded on the surf ...
Extracting linear structures, such as blood vessels or dendrites, from images is crucial in many medical imagery applications, and many handcrafted features have been proposed to solve this problem. However, such features rely on assumptions that are never ...
We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...
Institute of Electrical and Electronics Engineers2011
High quality CMOS image sensors are of great importance for LoC - Lab-on-Chip devices based on optical measurements. The main target in these devices is to minimize the cost and area while achieving a good resolution. The performance parameters of image se ...
This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...
In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...