Publications related to A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

Pierre-André Farine, Steve Tanner, Urs Alexander Müller

In this paper, the design of a low-noise amplifier (LNA) for a 32x32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10 μVrms, respectively, at a bandwidth of 66 kHz. The LNA consumes less than 85 μW. The integrated of ...

2011

Sampling Trajectories for Mobile Sensing

Martin Vetterli, Jayakrishnan Unnikrishnan

Classical sampling theory for sampling and reconstructing bandlimited fields in

\Re^d

addresses the problem of sampling on lattice points. We consider a generalization of this problem, in which one samples the field along

1

-dimensional spatial trajecto ...

2011

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to da ...

2011

Random Sampling ADC for Sparse Spectrum Sensing

Andreas Peter Burg

Scanning large bandwidths (spectrum sensing) pushes today’s analog hardware to its limits since periodic sampling at Nyquist rate with sufficient resolution is often prohibitively complex. In this paper, we consider a scenario where the signal to be acquir ...

2011

Low-distortion switched-capacitor event-driven analogue to-digital converter

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

An event-driven analogue-to-digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC nonlinearity, and reduces the swing and dynamic common-mode range requirement of the operational transconducta ...

Institution of Engineering and Technology2010

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome ...

EPFL2009

Phase–frequency detecting time-to-digital converter

Kyojin Choo

A simple time-to-digital converter (TDC), capable of detecting not only phase difference but also frequency difference, is presented. The proposed TDC guarantees pull-in even for PLLs with the lowest loop gain. The TDC is fabricated in a 65 nm CMOS process ...

2009

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

Seyed Armin Tajalli, Yusuf Leblebici, Zeynep Toprak Deniz, Omer Can Akgun, Thomas Liechti

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

IEEE2008

A Low-Rate Identification Method for Digital Predistorters Based on Volterra Kernel Interpolation

A novel identification and digital predistortion scheme of weakly nonlinear passband systems such as RF power amplifiers (PA) is presented. It is well known that for the identification of weakly nonlinear systems, despite the spectral regrowth, it suffices ...

2007

Sampling With Finite Rate of Innovation: Channel and Timing Estimation for UWB and GPS

Martin Vetterli, Irena Maravic

Abstract—In this work, we consider the problem of channel estimation by using the recently developed theory for sampling of signals with a finite rate of innovation [1]. We show a framework which allows for lower than Nyquist rate sampling applicable ...

2003

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

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Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

Sampling Trajectories for Mobile Sensing

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

Random Sampling ADC for Sparse Spectrum Sensing

Low-distortion switched-capacitor event-driven analogue to-digital converter

Parallel architecture for high-speed analog-to-digital conversion

Phase–frequency detecting time-to-digital converter

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

A Low-Rate Identification Method for Digital Predistorters Based on Volterra Kernel Interpolation

Sampling With Finite Rate of Innovation: Channel and Timing Estimation for UWB and GPS

Sampling Trajectories for Mobile Sensing

Random Sampling ADC for Sparse Spectrum Sensing

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

Parallel architecture for high-speed analog-to-digital conversion

Phase–frequency detecting time-to-digital converter

Sampling With Finite Rate of Innovation: Channel and Timing Estimation for UWB and GPS

A Low-Rate Identification Method for Digital Predistorters Based on Volterra Kernel Interpolation

Low-distortion switched-capacitor event-driven analogue to-digital converter

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology