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Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

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Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

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Adaptive simulation-based framework for error characterization of inexact circuits

Hardware / Software Architectural and Technological Exploration for Energy-Efficient and Reliable Biomedical Devices

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

An Accelerator for High Efficient Vision Processing

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Adaptive simulation-based framework for error characterization of inexact circuits

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

Hardware / Software Architectural and Technological Exploration for Energy-Efficient and Reliable Biomedical Devices

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

An Accelerator for High Efficient Vision Processing

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays