An Ultra-Low Power PPG and mm-Resolution ToF PPD-Based CMOS Chip Towards All-in-One Photonic Sensors
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Based on analogy between the charging and discharging of humans' tolerance to overheating stimuli and that of charge in an electrical capacitor, this paper proposes a simple mathematical model for predicting overheating risk given a set of measured / simul ...
In practice, some differences are usually observed between computer simulation and experimental results of a chaotic circuit. In this paper, it is tried to obtain computer simulation results having more correlation with those obtained in practice by using ...
Stress-induced changes in the imprint and switching behavior of (111)-oriented Pb(Zr,Ti)O-3 (PZT)-based capacitors have been studied using piezoresponse force microscopy. Visualization of polarization distribution and d(33)-loop measurements in individual ...
An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alt ...
Institute of Electrical and Electronics Engineers2013
Neural networks (NNs) implemented at the transistor level are powerful adaptive systems. They can perform hundreds of operations in parallel but at the expense of a large number of building blocks. In the case of analog realization, an extremely low chip a ...
Institute of Electrical and Electronics Engineers2011
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This paper presents a preliminary work on the feeding of an AC dipole using a resonant circuit with a varying resonant frequency. A single phase LC oscillator containing a variable capacitor is fed by a wide band amplifier or a voltage source inverter. For ...
Institute of Electrical and Electronics Engineers2011
For the past couple of decades the desire to add more complexity to a computer chip, while simultaneously reducing the cost per bit, has been accommodated by down-scaling. This approach has been extremely successful in the past, but like all good things it ...
EPFL2008
Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited for medium sampling frequencies (50-300MSPS) and medium resolutions, i.e. 8 to 14 bits. Having the lowest figure-of-merit (FOM) in its bandwidth and resoluti ...
EPFL2012
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An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC sta ...
2013
Cutting-edge CMOS neurochips, which consist of a Microelectrode Array (MEA) manufactured on top of CMOS circuitry, allow the recording of the electrical activity of neural networks in-vitro, and their stimulation. As CMOS technology continues to scale down ...
