High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Silicon transistor scaling is approaching its end and a transition to novel materials and device concepts is more than ever essential. High-mobility compound semiconductors are considered promising candidates to replace silicon, targeting low-power logic and high-speed electronics. However, to enable large scale and cost-effective integration, it is crucial to address the challenge of integrating III-V devices on silicon substrates and to ensure CMOS processing compatibility. In this work, possibilities and limitations of III-V-on-silicon electronics are explored experimentally. A material platform, suitable for 3D and co-planar integration of InGaAs-based devices with multiple functionalities and featuring CMOS compatible process modules is here presented. Scaled InGaAs FinFETs showing record high on-current of 350 µA/µm (IOFF = 100 nA/µm and VDD = 0.5 V), for III-V FETs on Si are demonstrated. Comparable device performance is also achieved in a 3D sequential integration fashion, where InGaAs transistor are fabricated on top of a Si CMOS device layer. The designed fabrication flow, targeting high-performance devices, can be adapted to the heterogeneous integration of multiple III-V compounds. Hence, following the same approach, the first sub-thermionic heterojunction InGaAs/GaAsSb Tunnel-FETs on silicon are reported. Tunnel-FETs belong to the category of steep-slope devices and can overcome MOSFET fundamental limitations taking advantage of quantum transport laws. In this work, some of the key technological challenges to fabricate III-V Tunnel-FETs are addressed and their impact on performance is experimentally demonstrated.

Graphene-based Field-effect Transistors

Adarsh Singh Sagar

With transistors set to reach their smallest possible size in the next decade, the silicon chip is likely to change dramatically, or be replaced entirely. The transistor industry's path which has been largely shaped by Gordon Moore's famous prediction that the number of transistors on a silicon chip would double approximately every eighteen months, predicts a size of transistor which silicon technology cannot sustain, thereby ushering in a post-silicon age in semiconductors soon. In this scenario, graphene-derived nanomaterials are emerging as promising candidates for post-silicon electronics devices, with potential applications as atomically thin transistors and other nanoelectronic devices which incorporate quantum size effects. However, such claims still require a few important issues to be addressed first . This thesis focuses on demonstrating and studying field effect behaviour in graphene- and graphite-based devices. It describes the differences between the two types of graphene bilayers and the effect of their stacking order when placed in an electric field. The differences are studied using Scanning Photocurrent Microscopy, leading to the conclusion that the bottom layer in a misoriented bilayer effectively screens the charge carrier modulation when used in a back-gated FET configuration. A polymer electrolyte gate was employed on top to ultilise the enhanced carrier mobility within the top layer. The study is extended from bilayer graphene to multilayer graphene (graphite) while addressing a possibility of fabricating a field effect transistor on such a material. The thesis comments on the differences between each of these and their prospects in future applications. While emphasizing the effect of the substrate in such FETs, an intrinsic gain in a graphene-based FET of over one is shown at room temperature. The importance of both these aspects in the devices is also elucidated. Furthermore, the misoriented bilayer transistors were incorporated into phase-shift detectors, to exhibit their functioning in logical circuits. On the technical side, a novel method for fabricating graphene-based transistors on a lab-scale has been demonstrated which uses fluorescence quenching to distinguish the number of layers in a graphene stack.

EPFL2011

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high-integration density, but also to replace thin-film transistors in large-area electronics. This thesis investigates the use of wet-chemically grown ZnO nanowires for the fabrication of high-performance, low-voltage field-effect transistors (FETs). The first part of this thesis addresses the electrical characteristics of the wet-chemically grown ZnO nanowires. The as-grown ZnO nanowires are highly conductive due to a large charge-carrier concentration caused by dopants unintentionally incorporated into the ZnO nanowires during the synthesis. This large charge-carrier concentration makes it difficult to modulate the conductivity of the nanowires by an external electric field, so that the as-grown wires are not suitable for FETs. A post-growth annealing step is employed to dramatically reduce the charge-carrier concentration of the nanowires which makes it possible to fabricate FETs with useful characteristics. ZnO-nanowire FETs in a global back-gate geometry based on annealed ZnO nanowires have a transconductance of 300 nS, an on/off current ratio of 107 and a subthrehold slope of 500 mV/decade. The maximum field-effect mobility of the annealed ZnO nanowires is around 50 cm2/Vs. An important requirement to obtain good FET characterisitcs is to minimize the influence of the source and drain contact resistance on the total device resistance. The material used for the source and drain contacts in this thesis is aluminum. It is demonstrated that the use of a plasma treatment in the contact regions prior to the evaporation of the aluminum contacts can greatly influence the contact properties between ZnO and aluminum. An argon-plasma treatment locally increases the charge-carrier concentration in the ZnO. It is shown that the doping effect of the argon-plasma treatment can be exploited to reduce the contact resistance between alumiunm and ZnO and improve the electrical performance of the FETs. In the second part of this thesis, the influence of the ambient air on the electrical characteristics of the ZnO-nanowire FETs is investigated. The electrical conductivity of the FETs is strongly affected by the distinct atmospheric conditions, which makes it difficult to obtain reliable FET characteristics. The potential of a self-assembled monolayer (SAM) based on fluoroalkylphosphonic acid molecules to passivate the ZnO nanowires against the undesirable effects of the ambient and to stabilize the electrical performance of ZnO-nanowire FETs is demonstrated. The stabilizing effect is attributed to the formation of a densely packed, hydrophobic SAM on the surface of ZnO and aluminum oxide. The quality of the hydrophobic SAMs is confirmed by means of water-contact-angle measurements on SAM-covered ZnO single crystals that show a contact angle of more than 110°. The third part of this thesis is dedicated to the fabrication of high-performance ZnO-nanowire FETs with patterned metal top-gate electrodes. A top-gate fabrication process is developed that uses a very thin gate dielectric consisting only of an alkylphosphonic acid SAM that can be deposited from solution. The insulating quality of the SAM is investigated for top-gate FETs that utilize either gold or aluminum for the top-gate electrode. Gold top-gate FETs show a transconductance of 1 µS, an on/off current ratio of 107, and a steep subthreshold slope of 90 mV/decade. The thin gate dielectric makes it possible to operate the gold top-gate FETs at low voltages of 1 V and simultaneously reduces the undesired gate current by more than three orders of magnitude compared to gold top-gate FETs that have been fabricated without a gate dielectric (MESFETs). The gate current of the gold top-gate FETs with SAM gate dielectric is as low as 1 pA for gate-source voltages between -1 V and 0.5 V. When aluminum is used for the top-gate electrode, a hybrid dielectric is formed at the interface between the SAM and the aluminum, consisting of the SAM and a spontaneously formed aluminum oxide layer. Owing to the hybrid gate dielectric, the aluminum top-gate FETs are operated with gate currents below 1 pA for voltages up to 3 V. The top-gate fabrication process does not require temperatures above 160 °C, which makes it possible to fabricate FETs on unconventional substrates that cannot tolerate high temperatures, such as glass or flexible plastics. Integrated circuits on single ZnO nanowires that are fabricated on glass and plastic substrates are demonstrated. The maximum switching frequency of the inverters is 1 MHz.

EPFL2011

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâs law. Modern digital integrated circuits contain billions of transistors, fabricated with CMOS technology. As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. Among the materials that are studied for charge-based devices, two-dimensional materials of the Transition Metal Di-Chalcogenides (TMDCs) family show promising opportunities, thanks to their electrical and physical properties. In order to enable 2D electronics to be integrated in the Back-End-Of-the-Line (BEOL) with conventional CMOS it is essential to attain complementary operation of the transistors, in order to achieve low standby power consumption. In CMOS, ions are physically implanted in silicon to create unipolar devices with Ohmic contacts. However, this process requires high annealing temperatures, which are not compatible with the low-thermal budget requirements for monolithic 3D integration. For 2D materials, physical doping, through ion-implantation, has not proven to be successful due to extreme thinness of the 2D semiconductors. The possibility of introducing dopant atoms during growth of the 2D material has been reported, but does not allow for any control of the doping profile. Several chemical and molecular doping techniques have been developed, but are non-stable and non-CMOS compatible. A device concept that does not rely on any physical or chemical doping, and use instead un-doped materials, would be of great interest in this regard. In this thesis, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer tungsten di-selenide. We show how modulation of the Schottky barriers at drain and source by a separate gate, named polarity gate, can enable the selection of the carriers injected in the channel, and achieve controllable polarity behaviour with ON/OFF current ratios > 1E6 for both electrons and holes conduction. Following this demonstration, we fabricate and characterize a variety of polarity-controllable logic gates such as Inverter, NAND, NOR, that are the building primitives used in the logic synthesis frameworks for conventional CMOS logic. Moreover, we experimentally show 2- and 3-Input XOR, and majority gates that, thanks to the polarity-controllable devices, can be realized with fewer transistors as compared to what is achievable in conventional CMOS. We demonstrate a complete standard cell library with the possibility of fabricating compact, highly-expressive logic gates that can be exploited to gain advantages at circuit level, using XOR and MAJ functions as logic primitives. Moreover, for the first time, we study scaling trends and evaluate the performances of polarity-controllable devices realized with undoped mono and bi-layer 2D materials. Using ballistic self-consistent quantum simulations combined with TCAD simulations, it is shown that, with the suitable channel material, such polarity-controllable technology can scale down to sub-10nm gate lengths, while showing performances comparable to the ones of unipolar, physically-doped 2D electronic devices.

EPFL2019

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

EPFL2011

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

EPFL2019

Graphene-based Field-effect Transistors

Adarsh Singh Sagar

EPFL2011