Real- and Q-space travelling: multi-dimensional distribution maps of crystal-lattice strain (epsilon(044)) and tilt of suspended monolithic silicon nanowire structures

Silicon nanowire-based sensors find many applications in micro- and nano-electromechanical systems, thanks to their unique characteristics of flexibility and strength that emerge at the nanoscale. This work is the first study of this class of micro- and nano-fabricated silicon-based structures adopting the scanning X-ray diffraction microscopy technique for mapping the in-plane crystalline strain (epsilon(044)) and tilt of a device which includes pillars with suspended nanowires on a substrate. It is shown how the micro- and nanostructures of this new type of nanowire system are influenced by critical steps of the fabrication process, such as electron-beam lithography and deep reactive ion etching. X-ray analysis performed on the 044 reflection shows a very low level of lattice strain (

Deep-ultraviolet-microelectromechanicaI systems stencils for high-throughput resistless. patterning of mesoscopic structures

Jürgen Brugger, Marc Antonius Friedrich van den Boogaart

We describe a combination of 100-mm wafer scale deep-ultraviolet (DUV) exposure and a microelectromechanical systems (MEMS) process to fabricate silicon nitride membranes with submicrometer apertures to be used as miniature shadow masks or nanostencils. Apertures down to a lateral resolution of 200 nm were made in a 500-nm-thick membrane by DUV exposure and dry plasma etching. The membranes were released by a combination of wet silicon etching using potassium hydroxide (KOH) and dry silicon etching using a plasma process. The millimeter-size stencils were used for single-step, local deposition of metal micro- and nano-patterns without the need for photoresist process steps. We have performed stencil deposition on full wafer scale for micro- and nano-patterns in a variety of metals (e.g. Al, Au, Ni, etc.). Dry under-etching of the nanowires resulted in free-standing cantilevered nanoelectromechanical systems (NEMS) structures with resonance frequencies in the megahertz range. The resistless method allows us to pattern micrometer and nanometer scale patterns in a single step without any further processing. It is promising for the surface processing of MEMS/NEMS devices having sensitive or fragile surfaces, such as biochips, organic polymer layers, and self-assembled monolayers. (C) 2004 American Vacuum Society.

2004

Characterisation and applications of stencil lithography

Jürgen Brugger, Nao Takano, Marc Antonius Friedrich van den Boogaart, Oscar Vazquez Mena

Increased flexibility of patterning methods is important for the engineering of multimaterial and multifunctional nano/micro-electro-mechanical systems (NEMS/MEMS), such as polymer-based electronic and sensor devices, 3D microfluidic systems, and bio-analytical systems. Stencil lithography is a good candidate as it is a resistless, single step patterning method based on direct, local deposition of material on an arbitrary surface through a solid-state membrane, e.g. a 200-nm thick silicon nitride (SiN) membrane. We present two new stencil membrane stabilisation geometries and associated MEMS processes that allow for advancing further towards a well-controlled full-wafer (100 mm) nanostencil process for reproducible, high-throughput, large-area nanopatterning of mesoscopic structures (10-9 - 10-3 m). In fact, the major challenges for well-controlled and reproducible nanostencil lithography are to control stress-induced membrane deformation, clogging of membrane apertures and the gap between stencil and substrate. The stabilized membranes show improved membrane stability (i.e. reduced out-of-plane deformation) up to 94%, resulting in an improved pattern definition of stencil-deposited structures. We have also systematically characterized the clogging of membrane apertures and the influence of the gap between stencil and substrate on the deposited structures as a function of aperture size and deposited material. A method is presented to recover nominal dimensions of stencil-deposited structures over a gap. To integrate nanomechanical structures with CMOS circuits, stencil lithography was used as a clean, CMOS-compatible method to define the mechanical structures on a CMOS circuit, using the stencildeposited metal patterns as a mask for silicon reactive ion etching (RIE). When the stencil and the CMOS wafer are put in contact, a gap exists between the layer to be structured and the stencil. We have been able to correct the blurring effect by developing a controlled dry Al etch process. The results obtained provide a clear remedy to overcome one of the major challenges in nanostencil-based surface patterning. Stencil lithography is also used in the development of novel nanotemplates of anodic porous alumina (APA). To obtain APA structures with high regularity, a method to pre-pattern the surface of the aluminum substrate before conventional anodization is a prerequisite. A pre-patterned arrangement of dots or holes on Al plates is obtained by evaporation, sputtering, electrodeposition, or chemical etching through stencils. It should result in a high regularity mono-domain APA with pore spacing comparable with the visible wavelength for large area photonic crystals for optical applications and luminescence devices.

2005

Copper / low-k technological platform for the fabrication of high quality factor above-IC passive devices

Modern communication devices demand challenging specifications in terms of miniaturization, performance, power consumption and cost. Every new generation of radio frequency integrated circuits (RF-ICs) offer better functionality at reduced size, power consumption and cost per device and per integrated function. Passive devices (resistors, inductors, capacitors, antennas and transmission lines) represent an important part of the cost and size of RF circuits. These components have not evolved at the same level of the transistor devices, especially because their performance is strongly degenerated when they scale down in size. The low resistivity silicon used to build the transistors also imposes prohibitive levels of RF losses to these passive devices. Radio frequency microelectromechanical systems (RF MEMS) are enabling technologies capable to bring significant improvement in the electrical performances and expressive size and cost reduction of these functions, with unparallel introduction of new functionalities, unimaginable to attain when using bulky, externally connected discrete components. High quality factor (Q) inductors are amongst ones of the most needed components in RF circuits and at the same time ones that are most affected by thin metallization and substrate related losses, demanding considerable research effort. This thesis presents a contribution toward the development of thick metal fabrication technologies, covering also the design, modeling and characterization of high quality factor and high self-resonant frequency (SRF) RF MEMS passive devices, with a special emphasis on spiral inductors. A new approach using damascene-like interconnect fabrication steps associated to low κ dielectrics (polyimide), highly-conductive thick copper electroplating, chemical mechanical polishing (CMP) and tailored substrate properties delivered quality factors in excess of 40 and self resonant frequencies in excess of 10 GHz, performances in the current state-of-the-art for integrated spiral inductors built on top of silicon wafers. Furthermore, the developed process steps are compatible with back-end processing used to fabricate modern IC interconnects and have a low thermal budget (< 250 °C), what makes it a good choice to build above-IC passives without degenerating the performance of passivated RF-CMOS circuits. Deep reactive ion etching (DRIE) of quartz substrates was also studied for the fabrication of spiral inductors, offering excellent RF performances (Q exceeding 40 and SRF exceeding 7 GHz). A new doubly-functional quartz packaging concept for RF MEMS devices was developed. This technique process both sides of the packaging wafer: the top is used to embed high quality factor copper inductors while the bottom is thermo-mechanically bonded to another RF MEMS wafer, offering a semi-hermetic SU-8 epoxy-based seal. The bonding process was optimized for high yield, to be compatible with SF6-plasma-released MEMS and to present low level of RF losses. Band pass filters for the GSM (1.8 GHz) and WLAN (5.2 GHz) standards were fabricated and characterized by RF measurements and full wave electromagnetic simulations. Although further development is need in order to predict the frequency response accurately, insertion losses as low as 1.2 dB were demonstrated, levels that cannot be usually attained using on-chip passives. Systematic analysis, RF measurements, electromagnetic simulations and equivalent circuit extraction were used to model the behavior of the fabricated devices and establish a methodology to deliver optimum performances for a given technological profile and specified performance targets (quality factor, inductance and frequency bandwidth). A simple yet accurate physics-based analytical model for spiral inductors was developed and proved to be accurate in terms of loss estimation for thick metal layers. This model is capable to accurately describe the frequency-dependent behavior of the device below its first resonant frequency over a large device design space. The model was validated by both measurements and full wave electromagnetic simulations and is well suited to perform numeric optimization of designs. The proposed models were also systematized in a Matlab® toolbox.

EPFL2007

Copper / low-k technological platform for the fabrication of high quality factor above-IC passive devices

EPFL2007

Characterisation and applications of stencil lithography

Jürgen Brugger, Nao Takano, Marc Antonius Friedrich van den Boogaart, Oscar Vazquez Mena

2005