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Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

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Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

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Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

An Ultra-Low Power NVM-Based Multi-Core Architecture for Embedded Bio Signal Processing

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Exploiting Circuit Duality to Speed Up SAT

Near-optimal thermal monitoring framework for many-core systems on chip

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Exploiting Circuit Duality to Speed Up SAT

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

An Ultra-Low Power NVM-Based Multi-Core Architecture for Embedded Bio Signal Processing

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Near-optimal thermal monitoring framework for many-core systems on chip