Increasing Functionality of III-V Nanowires on Silicon Substrates

Progress in nanotechnology, including fabrication and characterization tools, opened up the unprecedented low dimensional materials era, where we can manipulate and structure matter on a size scale that we could not reach before. Due to many interesting properties of nano-sized materials different from their bulk counterparts, we now have opportunities both in combining new material properties with existing technologies and in establishing new technologies. In this context, combining mature silicon technology with III-V compound semiconductors in order to utilise the advantages of both materials has been the main goal of this thesis. In hetero-epitaxial systems, there are difficulties associated with the lattice mismatch, polarity difference, and thermal expansion coefficient difference of the two materials that can lead to dislocations, anti-phase boundaries, strain, and even cracking. Among many other candidates in low dimensional materials system, one-dimensional nanowire is one of the most extensively investigated architectures to overcome most of these challenges thanks to the inherent small dimensions of interfaces and interesting electronic & photonic properties. Despite previous efforts in integrating GaAs nanowires with silicon in a position-controlled manner using a patterned dielectric mask, the fundamental understanding of nanowire growth mechanisms in the small openings was still missing. The core part of this work is dedicated to providing a clear pathway for realistic integration of III-Vs on silicon in the form of ordered nanowire arrays. I demonstrated that there is a critical aspect ratio of the pattern holes(diameter/height) which guarantees a high yield of vertical nanowires once we have well positioned Ga droplets prior to nanowire growth. We pointed out the importance of the initial GaAs crystal at the bottom of the pattern holes. A uniformly distributed initial nucleation along the oxide mask and silicon substrate line interface allows for vertical growth of nanowire and this understanding results in reproducible and high vertical yield (95%) of GaAs nanowire arrays on silicon. Having obtained reproducible growth of GaAs nanowire arrays, morphological properties of nanowires were investigated. A time series growth study revealed the length and diameter evolution in regular array systems. We found that increasing As4 flux can effectively narrow down the length distributions without degrading nanowire vertical yield. In addition, we could obtain ultrathin GaAs nanowire having diameters of 20 nm or even less in ordered array systems by taking advantage of the self-catalyzed growth method. Finally, electrical properties of silicon/GaAs nanowire heterojunctions were investigated with the goal of increasing their functionalities. Our preliminary study highlighted that we could effectively engineer Si/GaAs nanowire heterojunctions by in situ doping during the nanowire growth in the molecular beam epitaxy system.