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The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Related publications (54)

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Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz

This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

Ieee-Inst Electrical Electronics Engineers Inc2013

In the framework of the NanoTera project CabTuRes, a system-in-package for a nano-resonator was proposed, integrating CMOS driving electronics and vacuum encapsulation. This doctoral research aimed to investigate 3D-integration technologies for a Single-Wa ...

EPFL2013

Through Silicon Vias and thermocompression bonding using inkjet-printed gold nanoparticles for heterogeneous MEMS integration

Niels Quack

We present a novel technique for heterogeneous integration using gold filled Through Silicon Vias (TSV) and thermocompression bond bumps formed in a single fabrication step, using gold nanoparticles dispensed by inkjet printing. Gold-filled TSV arrays (12 ...

IEEE2013

High-temperature compatible 3D-integration processes for a vacuum-sealed CNT-based NEMS

Nico de Rooij, Danick Briand, Terunobu Akiyama, Rokhaya Gueye

A System-in-Package (SiP) concept for the 3D-integration of a Single Wall Carbon Nanotube (SWCNT) resonator with its CMOS driving electronics is presented. The key element of this advanced SiP is the monolithic 3D-integration of the MEMS with the CMOS elec ...

SPIE - International Society of Optical Engineering2013

Fabrication and formation of Ta/Pt-Si ohmic contacts applied to high-temperature Through Silicon Vias (TSVs)

Nico de Rooij, Danick Briand, Terunobu Akiyama, Rokhaya Gueye

Platinum/tantalum/silicon ohmic contacts were designed, fabricated and characterized to withstand high-temperature post-processing: the ohmic behavior was maintained after 1 h annealing, at temperatures up to 850 degrees C in an oxidizing environment. A LP ...

Elsevier2013

Design iterations on Lego R - like MEMS bricks

Titus Cieslewski

This semester project is a proof of concept for the production of Lego R -like bricks in MEMS. Several design iterations have been made using milimeter-scale, o-chip fabrication methods. The nal product consists of 3mmx6mmx2mm bricks made of PDMS enriched ...

2013

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

Fabrication and characterization of wafer-level deep TSV arrays

Michail Zervas, Yusuf Leblebici, Yüksel Temiz

Three Dimensional (3D) integration, based on through silicon vias (TSV), has the potential to become a key enabling technology for many applications. TSVs are commonly categorized according to their aspect ratio and diameter. An equally important parameter ...

IEEE2012

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Carlotta Guiducci, Michail Zervas, Yusuf Leblebici, Yüksel Temiz

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...

IEEE2012