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Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Related publications (39)

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FloDB: Unlocking Memory in Persistent Key-Value Stores

Rachid Guerraoui, Mihail Igor Zablotchi, Vasileios Trigonakis, Oana Maria Balmau

Log-structured merge (LSM) data stores enable to store and process large volumes of data while maintaining good performance. They mitigate the I/O bottleneck by absorbing updates in a memory layer and transferring them to the disk layer in sequential batch ...

2017

Calibration-free imaging through a multicore fiber using speckle scanning microscopy

Demetri Psaltis, Christophe Moser, Nicolino Stasio

The images produced by multicore endoscopes are pixe-lated, and their resolution is limited by the core-to-core spacing. Lenses can be used to improve the resolution, but this reduces the field of view proportionally. Lensless endoscopy through multicore f ...

Optical Society of America2016

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Since Damasio introduced the somatic markers hypothesis in Damasio (1994), it has spread through the psychological community, where it is now commonly acknowledged that somatic states are a factor in producing the qualitative dimension of our experiences. ...

Frontiers Research Foundation2015

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

This work explores support for region-based memory in Scala through macro-based domain-specific encoding that exploits a number of extensible language features such as implicits and value classes. ...

2015

Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...

Morgan & Claypool2014

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Muhammad Umer Khalid

Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, wh ...

Ieee2012

Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Ties Jan Henderikus Kluter

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption ...

EPFL2010

Stress effects on working memory, explicit memory, and implicit memory for neutral and emotional stimuli in healthy men

Maria del Carmen Sandi Perez

Stress is a strong modulator of memory function. However, memory is not a unitary process and stress seems to exert different effects depending on the memory type under study. Here, we explored the impact of social stress on different aspects of human memo ...

Frontiers Research Foundation2009

Mental time in amnesia: evidence from bilateral medial temporal damage before and after recovery

Olaf Blanke

The human mind is continuously involved in "projecting" the self in time in order to process past memories and predict future occurrences. "Self-projection" in time involves episodic and spatial memory, relying on medial-temporal structures, but also engag ...

Taylor & Francis2009