Publication
Silicon heterojunction (SHJ) solar cells have recently reached power conversion efficiencies above 25% with various device architectures and with industrial size (>200 cm(2)) wafers. Yet, for an accurate assessment of the efficiency potential and further development of the technology, the identification of high-performing device configurations, and their detailed analysis is still vital. In this work, we first present an overview of our lab-scale (4 cm(2)) front-junction cells based on n-type wafers with a 24.44% certified efficiency. We report on the key improvements compared with our previously reported devices (i.e., thinner front-side silicon layers and low refractive index rear reflector). Then, we present a detailed power loss analysis, showing that parasitic absorption in the front layer-stack remains a major source of loss despite the recent improvements. Accordingly, we investigate next approaches to circumvent this loss, such as localization of the highly absorbing front layers and switching to a rear-junction architecture. Using numerical calculations, we show that the front-junction configuration can benefit from an efficiency gain of 0.3%(abs) with contact localization if considerably low contact resistivities (