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Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Related publications (37)

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Near-Memory Data Services

Babak Falsafi

This column introduces seven invited position papers about the challenges and opportunities in near-data processing. "Near-Memory Data Services" by Babak Falsafi, "Automata Processing: The Memory Is the Processor!" by Mircea Stan, Kevin Skadron, "Overcomin ...

Institute of Electrical and Electronics Engineers2016

Scalable Metric Learning via Weighted Approximate Rank Component Analysis

François Fleuret, Cijo Jose

We are interested in the large-scale learning of Mahalanobis distances, with a particular focus on person re-identification. We propose a metric learning formulation called Weighted Approximate Rank Component Analysis (WARCA). WARCA optimizes the precision ...

Springer Int Publishing Ag2016

Charge-transport properties of monolayer MoS2 at the interface with dielectric materials

Simone Bertolazzi

Two-dimensional (2D) semiconductors, consisting of single-sheets of layered transition metal dichalcogenides (TMD), are attracting enormous interest from both fundamental science and technology. Monolayer molybdenum disulfide (MoS2), a typical example from ...

EPFL2015

Tunnel Field Effect Transistors

Arnab Biswas

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteri ...

EPFL2015

The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs

Mihai Adrian Ionescu, Montserrat Fernandez-Bolanos Badia, Elizabeth Buitrago Godinez, Sara Rigante

A 3D vertically stacked silicon nanowire (SiNW) and Fin field effect transistor (FET) featuring a high density array (7 or 8 x 20 SiNWs, > 4 Fins vertically stacked) of fully depleted, ultra-thin (SiNWs diameters similar to 15-30 nm, Fin width/height fw si ...

Elsevier2014

Towards Multi-Fabric 3D Integration Architectures

Panagiotis Athanasopoulos

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

Data Mapping for Unreliable Memories

Andreas Peter Burg, Georgios Karakonstantis, Christoph Studer

Future digital signal processing (DSP) systems must provide robustness on algorithm and application level to the presence of reliability issues that come along with corresponding implementations in modern semiconductor process technologies. In this paper, ...

2012

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Giovanni Antonio Salvatore

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...

EPFL2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

Fengda Sun

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis ...

EPFL2011