Publication
An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range
Related publications (44)
Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant
Minimally invasive monitoring of the electrical activity of specific cortical areas using implantable microsystems offers the promise of diagnosing neurological diseases, as well as detecting and identifying neural activity patterns which are specific to a ...
EPFL2012On-Chip Digital Background Calibration of Pipelined Analog-to-Digital Converters using Digital Assistance to support Nonlinear Residue Amplification
This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this ...
EPFL2012A 10-bit 50-MS/s Redundant SAR ADC with Split Capacitive-Array DAC
A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is ...
Springer Verlag2012Bits from Photons
The trends in the design of image sensors are to build sensors with low noise, high sensitivity, high dynamic range, and small pixel size. How can we benefit from pixels with small size and high sensitivity? In this dissertation, we study a new image senso ...
EPFL2012Ergodic Interference Alignment
This paper develops a new communication strategy, ergodic interference alignment, for the K-user interference channel with time-varying fading. At any particular time, each receiver will see a superposition of the transmitted signals plus noise. The standa ...
Institute of Electrical and Electronics Engineers2012A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor
The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are t ...
IEEE2012A Background Calibration Method for DAC Mismatch Correction in Multibit Sigma-Delta Modulators
Pierre-André Farine, Steve Tanner, Shafqat Ali
A topology for the calibration of DAC errors in multi-bit sigma delta modulators is presented. The proposed technique enables the calibration to proceed in the background. In this technique, two DACs are used in a time-interleaved fashion. One DAC is calib ...
2012A 16-channel 220 µW neural recording IC with embedded delta compression
Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar
A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...
2011Clock jitter estimation in noise
Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acqu ...
IEEE2011Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution
Seyed Armin Tajalli, Yusuf Leblebici
A current-mode analog-to-digital data converter (ADC) for biomedical readout front-end systems is being presented. The core of this circuit is a current-controlled ring oscillator (CCO) whose oscillation frequency is proportional to the inpu ...
2010