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Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

Related publications (44)

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This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

Low-power RF modeling of a 40nm CMOS technology using BSIM6

Christian Enz, Maria-Anna Chalkiadaki

The state-of-the-art scaled down CMOS processes have led to devices with extremely high Ft reaching several hundreds of GHz. This high F t can be traded with power consumption by moving the operating point towards weak inversion with Ft reaching tens of GH ...

2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

Development of a versatile low-power 24 GHz phased array front-end in 90 nm CMOS technology

Pierre-André Farine, Cyril Botteron, Christian Robert, Gabriele Tasselli, Saeed Ghamari, Ban Wang

This paper deals with the development of a four-channel low-power Phased Array Front-End (PhA-FE) at 24 GHz, targeting both low-power radar sensors and battery powered transceiver applications. Typically, PhA-FEs are power hungry architectures due to multi ...

IEEE2012

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Giovanni Antonio Salvatore

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid appro ...

EPFL2011

Single-photon Avalanche Diodes in sub-100nm Standard CMOS Technologies

Edoardo Charbon, Hyungjune Yoon, Mohammad Azim Karami

Single-photon avalanche diodes (SPADs) are evaluated in two sub-100nm CMOS technologies. Several geometries are implemented, whereas premature edge breakdown (PEB) prevention is achieved with n-well rings. The octagonal SPADs are implemented in 90nm and 65 ...

2011

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The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to incon ...

2011

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011