Publication
Over the years, several clock and data recovery architectures have been proposed for wireless Amplitude Shift Keying (ASK) transmitted signals. State-of-the-art architectures mainly rely on synchronous phase-locked loop circuits or selfsampling systems, both resulting in large area consumption. This work presents a novel CMOS architecture for Clock and Data Recovery (CDR) in miniaturised and wirelessly powered implants. The proposed CDR architecture works at 433.92 MHz and includes: an ASK-demodulator, an on-chip oscillator, a power-on-reset, a control and a recovering block operating in feedback-loop. The ASK-demodulator works for a data rate as high as 6Mbps and a modulation index in the range of 9-30%. A novel communication protocol is presented for a separated clock and data transmission. The entire CDR architecture occupies 17 x 89 mu m(2) and consumes 15.01 mu W while operating with a clock rate of 6 Mbps.