Publications related to Bringing NoCs to 65nm

Computational Imaging SPAD Cameras

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

EPFL2023

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

2D MoS2 Nanopores: Wafer-scale Fabrication and Monolayer Stability for Long-term Single-Molecule Sensing

Mukeshchand Thakur

Biologically inspired solid-state nanopores are artificial openings or apertures in thin membranes similar to natural protein ion channels in a lipid bilayer of cell membranes. In solid-state nanopores, a thin insulating membrane with single or multiple po ...

EPFL2022

Scalable fabrication of functional nanostructures on stretchable substrates by capillary-assisted particle assembly and adhesion lithography

Henry Shao-Chi Yu

The fabrication of metallic nanostructures on stretchable substrates enables specific applications that exploit the combination of the nano-scale phenomena and the mechanical tunability of the physical dimensions of the nanostructures. Due to the large dif ...

EPFL2022

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Mohamed Mostafa Sabry Aly, Halima Najibi

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

Embedded Microchannel Cooling for High Power-Density GaN-on-Si Power Integrated Circuits

Elison de Nazareth Matioli, Remco Franciscus Peter van Erp, Luca Nela, Georgios Kampitsis, Reza Soleiman Zadeh Ardebili

In this work, we demonstrate a new thermal management approach for direct cooling of GaN-on-Si power integrated circuits (ICs), in which the Si substrate functions as a microfluidic heat sink, turning Si into a cost-effective, high thermal performance subs ...

IEEE2020

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Elmira Shahrabi, Thomas La Grange, Yusuf Leblebici, Tugba Demirci

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

ReRAM From Material Study to CMOS Co-integration

Elmira Shahrabi

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...

EPFL2019

Three-Dimensional Nano-Acoustic Bragg Reflectors for CMOS Embedded NEMS

Luis Guillermo Villanueva Torrijo, Soumya Yandrapalli, David Ruffieux

Integration of CMOS electronic circuits and electromechanical resonators has been pursued for a long time by many different research groups and even foundries. This would improve the overall performance of electromechanical oscillators and sensors. However ...

Institute of Electrical and Electronics Engineers2017

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti, Nicholas Alexander Preyss

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017