Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region

In this work a double-gate pentacene TFT architecture is presented. The devices are fabricated on a polyimide substrate using three aligned levels of stencil lithography along with standard photolithography, which enable a soft yet well controlled device processing. The benefic impact of the top gate voltage control to reduce the leakage current and significantly improve the subthreshold swing of the device is demonstrated. Moreover, this original design show good promise for the enhancement of Ion/Ioff TEF characteristics.