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Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Related publications (30)

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Decoding electroencephalographic responses to visual stimuli compatible with electrical stimulation

Silvestro Micera, Simone Romeni, Laura Toni, Fiorenzo Artoni

Electrical stimulation of the visual nervous system could improve the quality of life of patients affected by acquired blindness by restoring some visual sensations, but requires careful optimization of stimulation parameters to produce useful perceptions. ...

Aip Publishing2024

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

Felix Schürmann, Pramod Shivaji Kumbhar, Omar Awile, Snehal Pramod Kumbhar, Ioannis Magkanaris

Advances in computational capabilities and large volumes of experimental data have established computer simulations of brain tissue models as an important pillar in modern neuroscience. Alongside, a variety of domain specific languages (DSLs) have been dev ...

ACM2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller

David Atienza Alonso, Miguel Peon Quiros, José Angel Miranda Calero, Simone Machetti, Pasquale Davide Schiavone, Thomas Christoph Müller, Rubén Rodríguez Álvarez, Benoît Walter Denkinger, Ruben Rodriguez, Saverio Nasturzio

In this work, we present eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP), a configurable and extendible single-core RISC-V-based ultra-low-power microcontroller. X-HEEP can be used standalone as a low-cost microcontroller, or it can be integrat ...

New York2023

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

EdgeAI-Aware Design of In-Memory Computing Architectures

Highly Parallel RTL Simulation

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Decoding electroencephalographic responses to visual stimuli compatible with electrical stimulation

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Graph Chatbot

EdgeAI-Aware Design of In-Memory Computing Architectures

Highly Parallel RTL Simulation

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Decoding electroencephalographic responses to visual stimuli compatible with electrical stimulation

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Green Cryptography and Other Optimisations

Green Cryptography and Other Optimisations